1. Field of the Invention
Example embodiments of the present invention relate generally to a boost voltage generating circuit and method thereof, and more particularly to a boost voltage generating circuit and method of operating said boost voltage generating circuit.
2. Description of the Related Art
Semiconductor memory devices, such as flash memory devices, may perform reading, programming and erasing operations. Different bias voltages may be applied to flash memory cells of the flash memory devices based on which operation is being performed.
FIG. 1A is a block diagram illustrating a conventional boost voltage generating circuit 10 which may provide a boost voltage to a semiconductor memory device. Referring to FIG. 1A, the conventional boost voltage generating circuit 10 may include a voltage comparator 11, an oscillator 12 and a pumping circuit 13.
FIG. 1B is a circuit diagram illustrating the voltage comparator 11 of FIG. 1A. Referring to FIG. 1B, resistors Rt and Rb may be provided to divide a boost voltage VPP to generate a divided voltage Vdet. The voltage comparator 11 may compare the divided voltage Vdet with a reference voltage Vref.
Referring to FIGS. 1A and 1B, the voltage comparator 11 may receive feedback of the boost voltage VPP created by the pumping circuit 13, may divide the boost voltage VPP and may compare the divided voltage Vdet with the reference voltage Vref. Based on the comparison result, the voltage comparator 11 may output a control signal OSCEN. The oscillator 12 may generate an oscillation signal in response to the control signal OSCEN. The pumping circuit 13 may generate the boost voltage VPP in response to the oscillation signal.
Referring to FIGS. 1A and 1B, if the boost voltage VPP rises above a threshold level, the voltage comparator 11 may output a control signal OSCEN at a disabled level (e.g., a second logic level, such as a lower logic level or logic “0”) as opposed to an enabled level (e.g., a first logic level, such as a higher logic level or logic “1”). In addition, the boost voltage VPP created by the pumping circuit 13 may cease increasing and may be maintained at a relatively stable level.
Referring to FIGS. 1A and 1B, if the boost voltage generating circuit 10 is used in a flash memory device, the boost voltage VPP and a first voltage (not shown) may be provided to a switch 20. The switch 20 may transfer a second voltage to a memory cell based on a memory operation mode (e.g., a reading mode, a programming mode, an erasing mode, etc.) of the flash memory device.
Referring to FIGS. 1A and 1B, in the programming mode of the flash memory device, if a source side hot carrier injection process is used, a current may be flow from the switch 20 towards memory cells of the flash memory device. Data signals D0 to Dn-1 may be input to n memory cells controlled by a single word line WL, and the current may flow via memory cells to which a data signal set to a second logic level (e.g., a lower logic level or logic “0”) may be input.
Referring to FIGS. 1A and 1B, the switch 20 may be a MOS transistor, and may have a resistive component if the MOS transistor is turned on. If the data signal set to the second logic level (e.g., a lower logic level or logic “0”) is input to the memory cells, and a current flowing from the switch 20 via the memory cells increases, the boost voltage VPP may be reduced due to the MOS transistor of the switch 20. As a result, a source line voltage VSL applied to the memory cells may be less than the boost voltage VPP provided by the boost voltage generating circuit 10.
FIG. 2 is a graph illustrating a boost voltage provided to a semiconductor memory device by the boost voltage generating circuit 10 of FIG. 1. Referring to FIG. 2, in the programming mode of the flash memory device of which the memory cells are controlled by a single word line WL, a voltage drop ΔV of the source line voltage VSL applied to a source line may increase as the number of memory cells to be programmed to store the data bit set to the second logic level (e.g., a lower logic level or logic “0”) increases, whereas the boost voltage VPP may remain substantially constant.
FIG. 3 is a circuit diagram illustrating a conventional boost voltage generating circuit. Referring to FIG. 3, the boost voltage generating circuit may include a block 40 which may generate a boost voltage VPP varying based on the number of memory cells to be programmed to store the data bit set to the second logic level (e.g., a lower logic level or logic “0”). The block 40 may be connected between a feedback boost voltage source VPP and a voltage comparator 11.
Referring to FIG. 3, the block 40 may control the boost voltage VPP, and may include a transistor group 41 having 32 NMOS transistors which may be respectively gated by data signals Data<31:0> and may be connected with one another in parallel, if the number of memory cells connected to a single word line WL is 32. Among the data signals Data<31:0>, if the data signal set to the second logic level (e.g., a lower logic level or logic “0”) increases, an equivalent resistance of the transistor group 41 may decrease. Thus, a current flowing through a plurality of resistors Rw, Rx, Ry and Rz may increase.
Referring to FIG. 3, if the current increases, a voltage drop caused by the respective resistors Rw, Rx, Ry and Rz may increase. Therefore, a voltage input to positive nodes of a comparator group 43 having a plurality of comparators (e.g., 3 comparators) may decrease. Accordingly, due to output signals of the comparator group 43, an equivalent resistance of a resistor group 44 connected between the boost voltage VPP and the voltage comparator 11 may decrease. In addition, as current that flows via the resistor group 44 and the voltage comparator 11 increases, a voltage signal Vdef input to a positive node of the voltage comparator 11 may decrease. If the voltage signal Vdef decreases with respect to the feedback boost voltage source VPP, a final boost voltage may increase.
In the conventional boost voltage generating circuit illustrated in FIG. 3, the voltage signal Vdet may change based on the number of the data signals set to the second logic level (e.g., a lower logic level or logic “0”) among memory cells to be programmed, by the unit of a multiple of eight. In other words, a turning on MOS transistors P1 to P3, included within the resistor group 44, may be controlled based on whether the number of the data signals set to the second logic level is equal to or less than 8, 16, 24, etc. (e.g., multiples of eight).
FIG. 4 is a graph illustrating a boost voltage provided to a semiconductor memory device by the boost voltage generating circuit of FIG. 3. Referring to FIG. 4, a generated boost voltage VPP may not increase linearly as the number of data signals set to the second logic level (e.g., a lower logic level or logic “0”) increases. Thus, a source line voltage VSL provided to a source line may decrease. Additional resistors and comparators may be included to limit a reduction to the source line voltage VSL, but adding circuitry may increase a cost and size of the semiconductor memory device. In addition, because a turn-on current of NMOS transistors included in the transistor group 41 may depend upon manufacturing processes or temperature, an increase of the boost voltage VPP may deteriorate in the programming mode of the memory cells.